ST STM32WL5 Series User Manual

RM0453 Rev 1 135/1461
RM0453 Embedded Flash memory (FLASH)
153
4.10.7 FLASH ECC register (FLASH_ECCR)
Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is ongoing. Word, half-word and
byte access.
Bits 9:3 PNB[6:0]: page number selection
These bits select the 2-Kbyte page to erase.
0x00: page 0
0x01: page 1
...
0x7F: page 127
Bit 2 MER: mass erase
When set, this bit triggers the mass erase (all user pages).
Bit 1 PER: page erase
0: page erase disabled
1: page erase enabled
Bit 0 PG: programming
0: Flash programming disabled
1: Flash programming enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD ECCC Res. CPUID[2:0] Res. ECCCIE Res. Res. Res. SYSF_ECC Res. Res. Res. ADDR_ECC[16]
rc_w1 rc_w1 r r r rw r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC[15:0]
r r rrrrr r rrr r rrr r
Bit 31 ECCD: ECC detection
Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is
generated.
This bit is cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
This bit is cleared by writing 1.
Bit 29 Reserved, must be kept at reset value.
Bits 28:26 CPUID[2:0]: CPU identification
Set by hardware. This bit indicates the Bus-ID of the CPU access causing the ECC failure.
000: CPUID for CPU1 bus ID value
001: CPUID for CPU2 bus ID value
Bit 25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English