RM0453 Rev 1 1061/1461
RM0453 Inter-integrated circuit (I2C) interface
1126
For I2C I/Os supporting 20mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 34.3: I2C implementation.
34.4.2 I2C pins and internal signals
34.4.3 I2C clock requirements
The I2C kernel is clocked by I2CCLK.
The I2CCLK period t
I2CCLK
must respect the following conditions:
t
I2CCLK
< (t
LOW
- t
filters
) / 4 and t
I2CCLK
< t
HIGH
with:
t
LOW
: SCL low time and t
HIGH
: SCL high time
t
filters:
when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x t
I2CCLK
.
The PCLK clock period t
PCLK
must respect the following condition:
t
PCLK
< 4/3 t
SCL
with t
SCL
: SCL period
Caution: When the I2C kernel is clocked by PCLK, this clock must respect the conditions for t
I2CCLK
.
Table 223. I2C input/output pins
Pin name Signal type Description
I2C_SDA Bidirectional I2C data
I2C_SCL Bidirectional I2C clock
I2C_SMBA Bidirectional SMBus alert
Table 224. I2C internal input/output signals
Internal signal name Signal type Description
i2c_ker_ck Input
I2C kernel clock, also named I2CCLK in this
document
i2c_pclk Input I2C APB clock
i2c_it Output
I2C interrupts, refer to Table 237: I2C Interrupt
requests for the full list of interrupt sources
i2c_rx_dma Output I2C receive data DMA request (I2C_RX)
i2c_tx_dma Output I2C transmit data DMA request (I2C_TX)
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