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ST STM32WL5 Series

ST STM32WL5 Series
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RM0453 Rev 1 455/1461
RM0453 Direct memory access controller (DMA)
479
13.3 DMA implementation
13.3.1 DMA1 and DMA2
DMA1 and DMA2 are implemented with the hardware configuration parameters shown
in Table 77.
13.3.2 DMA request mapping
The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the Section 14.3: DMAMUX
implementation.
Table 77. DMA1 and DMA2 implementation
Feature DMA1 DMA2
Number of channels 7 7
Security 1 (supported) 1 (supported)

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