RM0453 Rev 1 309/1461
RM0453 Reset and clock control (RCC)
364
7.4.6 RCC clock interrupt flag register (RCC_CIFR)
Address offset: 0x01C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 2 MSIRDYIE: MSI ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the MSI
oscillator stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the LSE
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 0 LSIRDYIE: LSI ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the LSI
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8765432 1 0
Res. Res. Res. Res. Res. Res.
LSE
CSSF
CSSF Res. Res.
PLL
RDYF
HSE
RDYF
HSI
RDYF
MSI
RDYF
LSE
RDYF
LSI
RDYF
r r rrrr r r
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSF: LSE CSS (clock security system) flag after masking
This bit is set by hardware when LSECSSIE = 1 and a failure is detected in the LSE
oscillator. It is cleared by software setting the LSECSSC bit.
0: No CSS interrupt caused by LSE clock failure
1: CSS interrupt caused by LSE clock failure
Bit 8 CSSF: HSE32 CSS flag
This bit is set by hardware when a failure is detected in the HSE32 oscillator. It is cleared by
software setting the CSSC bit.
0: No clock security interrupt caused by HSE32 clock failure
1: Clock security interrupt caused by HSE32 clock failure
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYF: PLL ready interrupt flag
This bit is set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by
software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
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