To Next Page

To Previous Page

Sub-GHz radio (SUBGHZ) RM0453

208/1461 RM0453 Rev 1

5.10.2 Sub-GHz radio generic packet control 1A register

(SUBGHZ_GPKTCTL1AR)

Address offset: 0x06B8

Reset value: 0x21

5.10.3 Sub-GHz radio generic whitening LSB register

(SUBGHZ_GWHITEINIRL)

Address offset: 0x06B9

Reset value: 0x00

Bit 7 Reserved, must be kept at reset value.

Bit 6 SBITSYNCEN: LoRa simple bit synchronization enable

This bit must be cleared to 0 when using generic packet and BPSK type.

0: simple bit synchronization disabled

1: simple bit synchronization enabled

Bit 5 RXDINV: LoRa receive data inversion

This bit must be cleared to 0 when using generic packet and BPSK type.

0: receive data not inverted

1: receive data inverted

Bit 4 BITSYNCDIS: LoRa normal bit synchronization enable

This bit must be cleared to 0 when using generic packet and BPSK type.

0: normal bit synchronization enabled

1: normal bit synchronization disabled

Bits 3:0 Reserved, must be kept at reset value.

76543210

Res. Res. SYNCDETEN CONTTX INFSEQSEL[1:0] INFSQEQEN WHITEINI[8]

rw rw rw rw rw rw

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 SYNCDETEN: Generic packet synchronization word detection enable

Bit 4 CONTTX: Generic packet continuous transmit enable

Bits 3:2 INFSEQSEL[1:0]: Generic packet infinite sequence selection

00: preamble 0x5555

01: all zero 0x0000

10: all one 0xFFFF

11: PRBS9

Bit 1 INFSQEQEN: Generic packet infinite sequence enable

Bit 0 WHITEINI[8]: Generic packet whitening initial value MSB bit [8]

76543210

WHITEINI[7:0]

rw rw rw rw rw rw rw rw

ST STM32WL5 Series User Manual

Questions and Answers: