Debug support (DBG) RM0453
1324/1461 RM0453 Rev 1
38 Debug support (DBG)
38.1 DBG introduction and main features
A comprehensive set of debug features is provided to support software development and
system integration:
• Independent breakpoint debugging of each CPU core in the system
• Code execution tracing
• Software instrumentation
• Cross-triggering
The debug features can be controlled via a JTAG/Serial-wire debug access port, using
industry standard debugging tools. A trace port allows data to be captured for logging and
analysis.
The debug features are based on Arm CoreSight™ components.
• General features:
– SWJ-DP: JTAG/Serial-wire debug port
– AHB-AP: AHB access port
• CPU1 debug features
– ROM table (see Section 38.8)
– System control space (SCS)
– Breakpoint unit (FPB) (see Section 38.9)
– Data watchpoint and trace unit (DWT) (see Section 38.6)
– Instrumentation trace macrocell (ITM) (see Section 38.10)
– Trace port interface unit (TPIU) (see Section 38.11)
– Cross trigger interface (CTI) (see Section 38.7)
• CPU2 debug features:
– ROM tables (see Section 38.13)
– System control space (SCS)
– Breakpoint unit (BPU) (see Section 38.14)
– Data watchpoint and trace unit (DWT) (see Section 38.6)
– Cross trigger interface (CTI) (see Section 38.7)
CPU1 debug features are accessible by the debugger via the CPU1 AHB-AP.
CPU2 debug features are accessible by the debugger via the CPU2 AHB-AP and its
associated AHB bus.
Additional information can be found in the Arm
®
documents referenced in Section 38.15.
Device level debug features are controlled in the DBGMCU (see Section 38.12), only
accessible by the CPU1.
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