Digital-to-analog converter (DAC) RM0453
614/1461 RM0453 Rev 1
19.7.11 DAC calibration control register (DAC_CCR)
Address offset: 0x38
Reset value: 0x00XX 00XX
19.7.12 DAC mode control register (DAC_MCR)
Address offset: 0x3C
Reset value: 0x0000 0000
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bit 12 Reserved, must be kept at reset value.
Bit 11 Reserved, must be kept at reset value.
Bits 10:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM1[4:0]
rw rw rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bits 20:5 Reserved, must be kept at reset value.
Bits 4:0 OTRIM1[4:0]: DAC channel1 offset trimming value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE1[2:0]
rw rw rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bits 23:16 Reserved, must be kept at reset value.
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
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