ST STM32WL5 Series User Manual

RM0453 Rev 1 439/1461
RM0453 System configuration controller (SYSCFG)
445
11.2.11 SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1)
Address offset: 0x100
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15IM EXTI14IM EXTI13IM EXTI12IM
EXTI11IM
EXTI10IM
EXTI9IM EXTI8IM EXTI7IM EXTI6IM EXTI5IM
Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RTCSSRUIM
Res.
RTCSTAMPTAMPLSECSSIM
rw rw
Bit 31 EXTI15IM: EXTI15 interrupt mask to CPU1
0: EXTI15 interrupt forwarded to CPU1
1. EXTI15 interrupt to CPU1 masked
Bit 30 EXTI14IM: EXTI14 interrupt mask to CPU1
Bit 29 EXTI13IM: EXTI13 interrupt mask to CPU1
Bit 28 EXTI12IM: EXTI12 interrupt mask to CPU1
Bit 27 EXTI11IM: EXTI11 interrupt mask to CPU1
Bit 26 EXTI10IM: EXTI10 interrupt mask to CPU1
Bit 25 EXTI9IM: EXTI9 interrupt mask to CPU1
Bit 24 EXTI8IM: EXTI8 interrupt mask to CPU1
Bit 23 EXTI7IM: EXTI7 interrupt mask to CPU1
Bit 22 EXTI6IM: EXTI6 interrupt mask to CPU1
Bit 21 EXTI5IM: EXTI5 interrupt mask to CPU1
Bits 20:3 Reserved, must be kept at reset value.
Bit 2 RTCSSRUIM: RTC SSRU interrupt mask to CPU1
0: RTC SSRU interrupt forwarded to CPU1
1. RTC SSRU interrupt to CPU1 masked
Bit 1 Reserved, must be kept at reset value.
Bit 0 RTCSTAMPTAMPLSECSSIM: RTCSTAMPTAMPLSECSS interrupt mask to CPU1
0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU1
1. RTCSTAMPTAMPLSECSS interrupt to CPU1 masked

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English