ST STM32WL5 Series User Manual

General-purpose timer (TIM2) RM0453
892/1461 RM0453 Rev 1
Address offset: 0x24
Reset value: 0x0000 0000
26.4.13 TIM2 counter [alternate] (TIM2_CNT)
Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in
TIMx_CR1 register:
• Previous section is for UIFREMAP = 0
• This section is for UIFREMAP = 1
Address offset: 0x24
Reset value: 0x0000 0000
26.4.14 TIM2 prescaler (TIM2_PSC)
Address offset: 0x28
Reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT[31:16]
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1514131211109876543210
CNT[15:0]
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Bits 31:0 CNT[31:0]: counter value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY CNT[30:16]
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CNT[15:0]
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Bit 31 UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register
Bits 30:0 CNT[30:0]: counter value
1514131211109876543210
PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English