Advanced-control timer (TIM1) RM0453
800/1461 RM0453 Rev 1
25.4.6 TIM1 event generation register (TIM1_EGR)
Address offset: 0x14
Reset value: 0x0000
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 25.4.3: TIM1 slave mode
control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. B2G BG TG COMG CC4G CC3G CC2G CC1G UG
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Bits 15:9 Reserved, must be kept at reset value.
Bit 8 B2G: Break 2 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt
can occur if enabled.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated.
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G: Capture/Compare 4 generation
Refer to CC1G description
Bit 3 CC3G: Capture/Compare 3 generation
Refer to CC1G description
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