ST STM32WL5 Series User Manual

RM0453 Rev 1 1049/1461
RM0453 Tamper and backup registers (TAMP)
1057
33.6.3 TAMP control register 3 (TAMP_CR3)
Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset: not affected
Bit 23 BKERASE: Backup registers
(1)
erase
Writing ‘1’ to this bit reset the backup registers
(1)
. Writing 0 has no effect. This bit is always
read as 0.
Bits 22:19 Reserved, must be kept at reset value.
Bit 18 TAMP3MSK: Tamper 3 mask
0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to
allow next tamper event detection.
1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by
hardware. The backup registers
(1)
are not erased.
The tamper 3 interrupt must not be enabled when TAMP3MSK is set.
Bit 17 TAMP2MSK: Tamper 2 mask
0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to
allow next tamper event detection.
1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by
hardware. The backup registers
(1)
are not erased.
The tamper 2 interrupt must not be enabled when TAMP2MSK is set.
Bit 16 TAMP1MSK: Tamper 1 mask
0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to
allow next tamper event detection.
1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by
hardware. The backup registers
(1)
are not erased.
The tamper 1 interrupt must not be enabled when TAMP1MSK is set.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3NOER: Tamper 3 no erase
0: Tamper 3 event erases the backup registers.
1: Tamper 3 event does not erase the backup registers
(1)
.
Bit 1 TAMP2NOER: Tamper 2 no erase
0: Tamper 2 event erases the backup registers.
1: Tamper 2 event does not erase the backup registers
(1)
.
Bit 0 TAMP1NOER: Tamper 1 no erase
0: Tamper 1 event erases the backup registers.
1: Tamper 1 event does not erase the backup registers
(1)
.
1. The device secrets erased by tamp_erase signal (refer to Table 218: TAMP interconnection).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res.
ITAMP8
NOER
Res.
ITAMP6
NOER
ITAMP5
NOER
Res.
ITAMP3
NOER
Res. Res.
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ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English