RM0453 Rev 1 447/1461
RM0453 Peripherals interconnect matrix
453
12.3 Interconnection details
12.3.1 From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2)
Purpose
Some timers are linked together internally for synchronization or chaining.
When one timer is configured in Master mode, it can reset, start, stop or clock the counter of
another timer configured in Slave mode. A description of the feature is provided in
Section 25.3.26: Timer synchronization.
The synchronization modes are detailed in the following sections:
• Section 25.3.26: Timer synchronization for advanced-control timers (TIM1)
• Section 26.3.18: Timers and external trigger synchronization for general-purpose
timers (TIM2)
Triggering signals
The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a
configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.
The input and output signals for TIM1 are shown in Figure 128: Advanced-control timer
block diagram.
The possible master/slave connections are given in tables below:
• Table 179: TIM1 internal trigger connection for TIM1
• Table 183: TIM2 internal trigger connection for TIM2
Active power modes
Run, Sleep, LPRun, LPSleep
COMP1 10 10 10 10 7 7 - - - - - - - -
COMP2 10 10 10 10 7 7
- - - - - - - -
SYST ERR 11
- 11 11 - - - - - - - - - -
1. Numbers in this table are links to corresponding subsections of Section 12.3: Interconnection details.
2. The “-” symbol in grayed cells means no interconnect.
Table 76. STM32WL5x peripherals interconnect matrix
(1)
(2)
(continued)
Source
Destination
TIM1
TIM2
TIM16
TIM17
LPTIM1
LPTIM2
LPTIM3
ADC
DAC
COMP1
COMP2
DMAMUX1
IRTIM
SUBGHZSPI
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