RM0453 Rev 1 1401/1461
RM0453 Debug support (DBG)
1448
38.10.3 ITM trace privilege register (ITM_TPR)
Address offset: 0xE00
Reset value: 0x0000 0000
38.10.4 ITM trace control register (ITM_TCR)
Address offset: 0xE80
Reset value: 0x0000 0000
Bits 31:0 STIMENA[31:0]: enable for stimulus port
Each bit n (31:0) enables the stimulus port associated with the ITM_STIMRn register.
0: Port disabled
1: Port enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIVMASK[31:16]
rrrrrrrrrrrrrrrr
1514131211109876543210
PRIVMASK[15:0]
rrrrrrrrrrrrrrrr
Bits 31:0 PRIVMASK[31:0]: Enables unprivileged access to ITM stimulus ports.
Each bit controls eight stimulus ports.
XXX0: Unprivileged access permitted on ports 0 to 7
XXX1: Only privileged access permitted on ports 0 to 7
XX0X: Unprivileged access permitted on ports 8 to 15
XX1X: Only privileged access permitted on ports 8 to 15
X0XX: Unprivileged access permitted on ports 16 to 23
X1XX: Only privileged access permitted on ports 16 to 23
0XXX: Unprivileged access permitted on ports 24 to 31
1XXX: Only privileged access permitted on ports 24 to 31
Note: PRIVMASK is a 32-bit value, the above listed values apply only on the lower 4 bits
(PRIVMASK[3:0]), with PRIVMASK[31:4] = 0xXXXXXXX.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res.
BUSY TRACEBUSID[6:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res.
TSPRESCALE[1:0]
Res. Res. Res.
SWOENA TXENA SYNCENA TSENA ITMENA
rw rw r rw rw rw rw
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