ST STM32WL5 Series

RM0453 Rev 1 1357/1461
RM0453 Debug support (DBG)
1448
38.6.12 DWT CoreSight peripheral identity register 4 (DWT_PIDR4)
Address offset: 0xFD0
Reset value: 0x0000 0004
Bit 9 LNK1ENA: enable for a second linked comparator
Indicates whether use of a second linked comparator is supported (read only).
0x1: Supported
Bit 8 DATAVMATCH: enable for cycle comparison.
0x0: Address comparison
0x1: Data value comparison
Bit 7 CYCMATCH: enable for cycle count comparison on comparator 0
This field is reserved for other comparators.
0x0: No cycle count comparison
0x1: Compares DWT_COMP0R with the cycle counter, DWT_CYCCNTR.
Bit 6 Reserved, must be kept at reset value.
Bit 5 EMITRANGE: Enables generation of data trace address offset packets (containing data
address bits 0 to 15).
0x0: Disabled
0x1: Enabled
Bit 4 Reserved, must be kept at reset value.
Bits 3:0 FUNCTION[3:0]: Selection of action to take on comparator match
The meaning of this bit field depends on the setting of the DATAVMATCH and CYCMATCH
fields. See [5].
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. F4KCOUNT[3:0] JEP106CON[3:0]
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Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 F4KCOUNT[3:0]: register file size
0x0: Register file occupies a single 4-Kbyte region.
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
0x4: Arm
®
JEDEC code