ST STM32WL5 Series User Manual

Reset and clock control (RCC) RM0453
352/1461 RM0453 Rev 1
7.4.43 RCC CPU2 APB1 peripheral clock enable in Sleep mode register 1
(RCC_C2APB1SMENR1)
Address offset: 0x178
Reset value: 0xA0E2 4401
Access: no wait state, word, half-word and byte access
Bit 17 AESSMEN: AES accelerator clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: AES clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: AES clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2
CStop mode
Bit 16 PKASMEN: PKA accelerator clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: PKA clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: PKA clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2
CStop mode
Bits 15:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
SMEN
Res.
DAC
SMEN
Res. Res. Res. Res. Res.
I2C3
SMEN
I2C2
SMEN
I2C1
SMEN
Res. Res. Res.
USART2
SMEN
Res.
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
SPI2S2
SMEN
Res. Res. Res.
RTC
APB
SMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM2
SMEN
rw rw rw
Bit 31 LPTIM1SMEN: Low-power timer 1 clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: LPTIM1 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: LPTIM1 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACSMEN: DAC clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: DAC clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: DAC clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2
CStop mode
Bits 28:24 Reserved, must be kept at reset value.
Bit 23 I2C3SMEN: I2C3 clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: I2C3 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: I2C3 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English