Debug support (DBG) RM0453
1406/1461 RM0453 Rev 1
38.10.12 ITM CoreSight component identity register 2 (ITM_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
38.10.13 ITM CoreSight component identity register 3 (ITM_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
38.10.14 CPU1 ITM register map and reset values
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
Table 280. CPU1 ITM register map and reset values
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000 to
0x07C
ITM_STIM0-31R STIMULUS[31:0]
Reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
0x080
ITM_TER STIMENA[31:0]
Reset value 00000000000000000000000000000000
0x084 to
0xDCC
Reserved Reserved.
0xE00
ITM_TPR PRIVMASK[31:0]
Reset value 00000000000000000000000000000000
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