RM0453 Rev 1 1399/1461
RM0453 Debug support (DBG)
1448
Refer to Section 38.8: CPU1 ROM table for the register boundary addresses.
38.10 CPU1 instrumentation trace macrocell (ITM)
The ITM generates trace information as packets. There are three sources that can generate
packets. If multiple sources generate packets at the same time, the ITM arbitrates the order
in which packets are output. The three sources in decreasing order of priority are:
0x004
FPB_REMAPR
Res.
Res.
RMPSP
REMAP[23:0]
Res.
Res.
Res.
Res.
Res.
Reset value 1000000000000000000000000
0x008 to
0x024
FPB_COMP0-7R
REPLACE[1:0]
Res.
COMP[26:0]
Res.
ENABLE
Reset value 00 000000000000000000000000000 0
0x028 to
0xFCC
Reserved Reserved.
0xFD0
FPB_PIDR4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
F4KCOUNT
[3:0]
JEP106CON
[3:0]
Reset value 00000100
0xFD4 to
0xFDC
Reserved Reserved.
0xFE0
FPB_PIDR0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PARTNUM[7:0]
Reset value 00000011
0xFE4
FPB_PIDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
JEP106ID
[3:0]
PARTNUM
[11:8]
Reset value 10110000
0xFE8
FPB_PIDR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REVISION
[3:0]
JEDEC
JEP106ID
[6:4]
Reset value 00101011
0xFEC
FPB_PIDR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REVAND[3:0] CMOD[3:0]
Reset value 00000000
0xFF0
FPB_CIDR0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[7:0]
Reset value 00001101
0xFF4
FPB_CIDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CLASS[3:0]
PREAMBLE
[11:8]
Reset value 11100000
0xFF8
FPB_CIDR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[19:12]
Reset value 00000101
0xFFC
FPB_CIDR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[27:20]
Reset value 10110001
Table 279. CPU1 FPB register map and reset values (continued)
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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