Reset and clock control (RCC) RM0453
346/1461 RM0453 Rev 1
7.4.37 RCC CPU2 APB1 peripheral clock enable register 2
(RCC_C2APB1ENR2)
Address offset: 0x15C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2S2EN: CPU2 SPI2S2 clock enable
This bit is set and cleared by software.
0: SPI2S2 clock disabled for CPU2
1: SPI2S2 clock enabled for CPU2
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 RTCAPBEN: CPU2 RTC APB bus clock enable
This bit is set and cleared by software. RTC kernel clock is controlled by the RTCEN bit in
the RCC_BDCR register.
0: RTC APB bus clock disabled for CPU2
1: RTC APB bus clock enabled for CPU2
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 TIM2EN: CPU2 TIM2 timer clock enable
This bit is set and cleared by software.
0: TIM2 clock disabled for CPU2
1: TIM2 clock enabled for CPU2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPTIM3
EN
LPTIM2
EN
Res. Res. Res. Res.
LP
UART1
EN
rw rw rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3EN: CPU2 low-power timer 3 clocks enable
This bit is set and cleared by software.
0: LPTIM3 bus and kernel clocks disabled for CPU2
1: LPTIM3 bus and kernel clocks enabled for CPU2
To Next Page
Loading...
Need help?
General
