Sub-GHz radio (SUBGHZ) RM0453
216/1461 RM0453 Rev 1
5.10.27 Sub-GHz radio power control register (SUBGHZ_PCR)
Address offset: 0x091A
Reset value: 0x50
This register is retained in Sleep mode but lost in Deep-Sleep mode.
5.10.28 Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R)
Address offset: 0x0923
Reset value: 0x06
This register is retained in Sleep mode but lost in Deep-Sleep mode.
76543210
Res. CLE CLV[1:0] Res. Res. Res. Res.
rw rw rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 CLE: Power-supply current limiter enable
0: power-supply current limiter disabled (unlimited current)
1: power-supply current limiter enabled (current limited according to CLV[1:0])
Bits 5:4 CLV[1:0]: Power-supply current limiter value
When the power-supply current limiter is enabled by CLEN, these bits define the maximum
current limiting level.
0x0: power-supply current limiting level 25 mA
0x1: power-supply current limiting level 50 mA (default)
0x2: power-supply current limiting level 100 mA
0x3: power-supply current limiting level 200 mA
Bits 3:0 Reserved, must be kept at reset value.
76543210
Res Res Res Res Res DRV[1:0] Res
rw rw
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:1 DRV[1:0]: SMPS maximum drive capability.
0x0: 20 mA
0x1: 40 mA
0x2: 60 mA
0x3: 100 mA (default)
Bit 0 Reserved, must be kept at reset value.
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