RM0453 Rev 1 823/1461
RM0453 Advanced-control timer (TIM1)
829
25.4.27 TIM1 alternate function option register 1 (TIM1_AF1)
Address offset: 0x60
Reset value: 0x0000 0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2]
rw rw
1514131211109876543210
ETRSEL[1:0] Res. Res.
BK
CMP2P
BK
CMP1P
BKINP Res. Res. Res. Res. Res. Res.
BK
CMP2E
BK
CMP1E
BKINE
rw rw rw rw rw rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: ETR source selection
These bits select the ETR input source.
0000: ETR legacy mode
0001: COMP1 output
0010: COMP2 output
Others: Reserved
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 BKCMP2P: BRK COMP2 input polarity
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
1: COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 10 BKCMP1P: BRK COMP1 input polarity
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
1: COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 9 BKINP: BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1)
1: BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bits 8:3 Reserved, must be kept at reset value.
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