Low-power universal asynchronous receiver transmitter (LPUART) RM0453
1254/1461 RM0453 Rev 1
36.7.6 LPUART request register (LPUART_RQR)
Address offset: 0x18
Reset value: 0x0000 0000
36.7.7 LPUART interrupt and status register [alternate] (LPUART_ISR)
Address offset: 0x1C
Reset value: 0x0080 00C0
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
151413121110987654321 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFRQ RXFRQ MMRQ SBKRQ Res.
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Bits 31:5 Reserved, must be kept at reset value.
Bit 4 TXFRQ: Transmit data flush request
This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This
sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register).
Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in
order to ensure that no data are written in the data register.
Bit 3 RXFRQ: Receive data flush request
Writing 1 to this bit clears the RXNE flag.
This enables discarding the received data without reading it, and avoid an overrun condition.
Bit 2 MMRQ: Mute mode request
Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag.
Bit 1 SBKRQ: Send break request
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
Note: If the application needs to send the break character following all previously inserted
data, including the ones not yet transmitted, the software should wait for the TXE flag
assertion before setting the SBKRQ bit.
Bit 0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TXFT RXFT Res. RXFF TXFE REACK TEACK WUF RWU SBKF CMF BUSY
rr rrrrrrrrr
1514131211109876543210
Res. Res. Res. Res. Res. CTS CTSIF Res. TXFNF TC RXFNE IDLE ORE NE FE PE
rr rrrrrrrr
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