Power control (PWR) RM0453
222/1461 RM0453 Rev 1
The inrush current of the LDO and SMPS step-down converter can be controlled via the
sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz
radio Deep-Sleep mode. For more details see Section 5: Sub-GHz radio (SUBGHZ).
The SMPS needs a clock to be functional. If for any reason this clock stops, the device may
be destroyed. To avoid this situation, a clock detection is used to, in case of a clock failure,
switch off the SMPS and enable the LDO. The SMPS clock detection is enabled by the sub-
GHz radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled
and must be enabled before enabling the SMPS. For more details, see Section 5: Sub-GHz
radio (SUBGHZ).
Danger: Before enabling the SMPS, the SMPS clock detection must be
enabled in the sub-GHz radio SUBGHZ_SMPSC0R.CLKDE.
6.1.1 Independent analog peripherals supply
To improve the ADC conversion accuracy and to extend the supply flexibility, the analog
peripherals have an independent power supply that can be separately filtered and shielded
from noise on the PCB.
The analog peripherals voltage supply input is available on a separate VDDA pin.
An isolated supply ground connection is provided on VSSA
pin.
The V
DDA
supply voltage can be different from V
DD
. The presence of V
DDA
must be checked
before enabling any of the analog peripherals supplied by V
DDA
(A/D converter,
comparators, voltage reference buffer).
The V
DDA
supply can be monitored by the peripheral voltage monitoring, and compared with
a threshold (1.65 V for PVM3). See Section 6.2.3: Peripheral voltage monitoring (PVM) for
more details.
When a single supply is used, V
DDA
can be externally connected to V
DD
through the
external filtering circuit in order to ensure a noise-free V
DDA
reference voltage.
ADC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a
separate reference voltage lower than V
DDA
, to V
REF+
. V
REF+
is the highest voltage,
represented by the full scale value, for an analog input (ADC) signal.
V
REF+
can be provided either by an external reference of by an internal buffered voltage
reference (VREFBUF).
The internal voltage reference is enabled by setting the ENVR bit in the VREFBUF control
and status register (VREFBUF_CSR). The voltage reference is set to 2.5 V when the VRS
bit is set and to 2.048 V when the VRS bit is cleared. The internal voltage reference can also
provide the voltage to external components through V
REF+
pin. Refer to the device
datasheet and to Voltage reference buffer (VREFBUF) for further information.
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