Reset and clock control (RCC) RM0453
316/1461 RM0453 Rev 1
7.4.13 RCC APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x040
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3RST: Low-power timer 3 reset
This bit is set and cleared by software.
0: No effect
1: LPTIM3 reset
Bit 5 LPTIM2RST: Low-power timer 2 reset
This bit is set and cleared by software.
0: No effect
1: LPTIM2 reset
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1RST: Low-power UART 1 reset
This bit is set and cleared by software.
0: No effect
1: LPUART1 reset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM17
RST
TIM16
RST
Res.
rw rw
1514131211109876543210
Res.
USART1
RST
Res.
SPI1
RST
TIM1
RST
Res.
ADC
RST
Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: Timer 17 reset
This bit is set and cleared by software.
0: No effect
1: TIM17 reset
Bit 17 TIM16RST: Timer 16 reset
This bit is set and cleared by software.
0: No effect
1: TIM16 reset
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
This bit is set and cleared by software.
0: No effect
1: USART1 reset
Bit 13 Reserved, must be kept at reset value.
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