RM0453 Rev 1 597/1461
RM0453 Digital-to-analog converter (DAC)
618
19.4.4 DAC data format
Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
• Single DAC channel
There are three possibilities:
– 8-bit right alignment: the software has to load data into the DAC_DHR8R1[7:0] bits
(stored into the DHR1[11:4] bits)
– 12-bit left alignment: the software has to load data into the DAC_DHR12L1 [15:4]
bits (stored into the DHR1[11:0] bits)
– 12-bit right alignment: the software has to load data into the DAC_DHR12R1 [11:0]
bits (stored into the DHR1[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHR1 (data holding registerx, which are internal non-
memory-mapped registers). The DHR1 register is then loaded into the DOR1 register either
automatically, by software trigger or by an external event trigger.
Figure 87. Data registers in single DAC channel mode
19.4.5 DAC conversion
The DAC_DOR1 cannot be written directly and any data transfer to the DAC channel1 must
be performed by loading the DAC_DHR1 register (write operation to DAC_DHR8R1,
DAC_DHR12L1, DAC_DHR12R1, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD).
Data stored in the DAC_DHR1 register are automatically transferred to the DAC_DOR1
register after one dac_pclk clock cycle, if no hardware trigger is selected (TEN1 bit in
DAC_CR register is reset). However, when a hardware trigger is selected (TEN1 bit in
DAC_CR register is set) and a trigger occurs, the transfer is performed three dac_pclk clock
cycles after the trigger signal.
When DAC_DOR1 is loaded with the DAC_DHR1 contents, the analog output voltage
becomes available after a time t
SETTLING
that depends on the power supply voltage and the
analog output load.
31 24 15 7 0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710b
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