Reset and clock control (RCC) RM0453
354/1461 RM0453 Rev 1
7.4.44 RCC CPU2 APB1 peripheral clock enable in Sleep mode register 2
(RCC_C2APB1SMENR2)
Address offset: 0x17C
Reset value: 0x0000 0061
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPTIM3
SMEN
LPTIM2
SMEN
Res. Res. Res. Res.
LP
UART1
SMEN
rw rw rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3SMEN: Low-power timer 3 clocks enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: LPTIM3 bus and kernel clocks disabled by the clock gating during CPU2 CSleep and
CStop modes
1: LPTIM3 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
Bit 5 LPTIM2SMEN: Low power timer 2 clocks enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: LPTIM2 bus and kernel clocks disabled by the clock gating during CPU2 CSleep and
CStop modes
1: LPTIM2 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1SMEN: Low power UART 1 clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: LPUART1 bus clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: LPUART1 bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
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