ST STM32WL5 Series User Manual

RM0453 Rev 1 667/1461
RM0453 AES hardware accelerator (AES)
698
CTR encryption and decryption
Figure 116 and Figure 117 describe the CTR encryption and decryption process,
respectively, as implemented in the AES peripheral. The CTR mode is selected by writing
010 to the CHMOD[2:0] bitfield of AES_CR register.
Figure 116. CTR encryption
Figure 117. CTR decryption
In CTR mode, the cryptographic core output (also called keystream) Ox is XOR-ed with
relevant input block (Px' for encryption, Cx' for decryption), to produce the correct output
block (Cx' for encryption, Px' for decryption). Initialization vectors in AES must be initialized
as shown in Table 134.
Table 134. CTR mode initialization vector definition
AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]
Nonce[31:0] Nonce[63:32] Nonce[95:64] 32-bit counter = 0x0001
MSv19102V3
Encrypt
AES_KEYRx (KEY)
AES_DINR (plaintext P1)
AES_DOUTR (ciphertext C1)
DATATYPE[1:0]
Swap
management
input
output
Legend
XOR
Swap
management
DATATYPE[1:0]
Encrypt
AES_KEYRx (KEY)
AES_DOUTR (ciphertext C2)
DATATYPE[1:0]
Swap
management
Swap
management
DATATYPE[1:0]
Counter
increment (+1)
AES_DINR (plaintext P2)
I1
I2
O1 O2
Block 1 Block 2
P1'
P2'
C1'
C2'
AES_IVRx
Nonce + 32-bit counter (+1)
AES_IVRx
Nonce + 32-bit counter
MSv18942V2
Encrypt
AES_KEYRx (KEY)
AES_DINR (ciphertext C1)
AES_DOUTR (plaintext P1)
DATATYPE[1:0]
Swap
management
AES_IVRx
Nonce + 32-bit counter
input
output
Legend
XOR
Swap
management
DATATYPE[1:0]
Encrypt
AES_KEYRx (KEY)
AES_DOUTR (plaintext P2)
DATATYPE[1:0]
Swap
management
AES_IVRx
Nonce + 32-bit counter (+1)
Swap
management
DATATYPE[1:0]
Counter
increment (+1)
AES_DINR (ciphertext C2)
I1
I2
O1 O2
Block 1 Block 2
C1'
C2'
P1'
P2'

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English