Global security controller (GTZC) RM0453
92/1461 RM0453 Rev 1
3.6 GTZC TZIC registers
All GTZC TZIC registers are accessed by words (32-bit), halfwords (16-bit) and bytes (8-bit).
3.6.1 GTZC TZIC interrupt enable register 1 (GTZC_TZIC_IER1)
Address offset: 0x000
Reset value: 0xFFFF FFFF
when security is enabled (ESE = 1)
Reset value: 0x0000 0000
when security is disabled (ESE = 0)
This register can only be access by a secure privileged access for read and write.
A non-secure or unprivileged access is ignored and return zero data, and an illegal access
event is generated.
Note: When the system is non-secure (ESE = 0), this register cannot be written and is read zero.
No illegal access interrupt is generated.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. PKAIE
SRAM2
IE
SRAM1
IE
FLASH
IE
DMAM
UX1IE
DMA2
IE
DMA1
IE
FLASH
IFIE
PWRIE
SUBG
HZSP
IIE
RNGIE AESIE
TZSC
IE
TZICIE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PKAIE: Illegal access event interrupt enable bit for PKA
0: Disabled (masked)
1: Enabled (unmasked)
Bit 12 SRAM2IE: Illegal access event interrupt enable bit for SRAM2
0: Disabled (masked)
1: Enabled (unmasked)
Bit 11 SRAM1IE: Illegal access event interrupt enable bit for SRAM1
0: Disabled (masked)
1: Enabled (unmasked)
Bit 10 FLASHIE: Illegal access event interrupt enable bit for Flash memory
0: Disabled (masked)
1: Enabled (unmasked)
Bit 9 DMAMUX1IE: Illegal access event interrupt enable bit for DMAMUX1
0: Disabled (masked)
1: Enabled (unmasked)
Bit 8 DMA2IE: Illegal access event interrupt enable bit for DMA2
0: Disabled (masked)
1: Enabled (unmasked)
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