RM0453 Rev 1 247/1461
RM0453 Power control (PWR)
276
When exiting the Stop 0 mode, the MCU is either in Run mode (range 1 or range 2
depending on VOS bit in PWR control register 1 (PWR_CR1)) or in LPRun mode if the bit
LPR is set in the same register.
6.5.8 Stop 1 mode
The Stop 1 mode is the same as Stop 0 mode except that the main regulator is off, and only
the low-power regulator is on. Stop 1 mode can be entered from Run mode and from LPRun
mode. The device only enters Stop 1 mode once the low-power regulator is ready. The
Table 51. Stop 0 mode
Stop 0 Description
Mode entry
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP bit is set in Cortex system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = 0b000 in PWR_CR1 and/or PWR_C2CR1 or higher
On return from ISR while:
– SLEEPDEEP bit is set in Cortex system control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = 0b000 in PWR_CR1 and/or PWR_C2CR1 or higher
Note: To enter Stop 0 mode, all EXTI line pending bits (in EXTI pending register
(EXTI_PR1), and EXTI pending register (EXTI_PR2)), and the peripheral
flags generating wakeup interrupts must be cleared. Otherwise, the Stop 0
mode entry procedure is ignored and program execution continues.
Mode exit
If WFI or return from ISR was used for entry
Any EXTI line configured in Interrupt mode (the corresponding EXTI interrupt
vector must be enabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wakeup capability. Refer to Table 89: CPU1 vector
table, and Table 90: CPU2 vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI line configured in event mode. Refer to Table 93: Wakeup interrupts.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI line configured in Interrupt mode (even if the corresponding EXTI
interrupt vector is disabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wakeup capability. Refer toTable 89: CPU1 vector
table, and Table 90: CPU2 vector table.
Wakeup event: refer to Table 93: Wakeup interrupts.
Wakeup latency
Longest wakeup time between: MSI or HSI16 wakeup time and Flash memory
wakeup time from Stop 0 mode.
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