ST STM32WL5 Series User Manual

Direct memory access controller (DMA) RM0453
454/1461 RM0453 Rev 1
13 Direct memory access controller (DMA)
13.1 Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
There are two instances of DMA, DMA1 and DMA2.
Each channel is dedicated to managing memory access requests from one or more
peripherals. Each DMA includes an arbiter for handling the priority between DMA requests.
13.2 DMA main features
• Single AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 2
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• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
• Security support:
– Support for AHB secure and non-secure DMA transfers, independently of a first
channel level, and independently at a source and destination sub-level
– Security-aware AHB slave port, protecting any secure resource (register, register
field) from a non-secure software access
• Privileged/unprivileged support:
– Support for AHB privileged and unprivileged DMA transfers, independently of a
channel level
– Privileged-aware AHB slave port

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English