Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0453
1320/1461 RM0453 Rev 1
Reset value: 0x0000
37.9.8 SPIx_I2S configuration register (SPIx_I2SCFGR)
Address offset: 0x1C
Reset value: 0x0000
1514131211109876543210
TXCRC[15:0]
rrrrrrrrrrrrrrrr
Bits 15:0 TXCRC[15:0]: Tx CRC register
When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1
is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPIx_CRCPR register.
Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
(CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8
standard.
The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
(CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY flag is set could return an incorrect value.
These bits are not used in I
2
S mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res.
ASTR
TEN
I2SMOD I2SE I2SCFG[1:0] PCMSYNC Res. I2SSTD[1:0] CKPOL DATLEN[1:0] CHLEN
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 ASTRTEN: Asynchronous start enable.
0: The Asynchronous start is disabled.
When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is
received and an appropriate transition is detected on the WS signal.
1: The Asynchronous start is enabled.
When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is
received and the appropriate level is detected on the WS signal.
Note: The appropriate transition is a falling edge on WS signal when I
2
S Philips Standard is used,
or a rising edge for other standards.
The appropriate level is a low level on WS signal when I
2
S Philips Standard is used, or a high
level for other standards.
Please refer to Section 37.7.3: Start-up description for additional information.
Bit 11 I2SMOD: I2S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI is disabled.
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