Debug support (DBG) RM0453
1422/1461 RM0453 Rev 1
38.12.3 DBGMCU CPU1 APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1)
Address offset: 0x03C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_
LPTIM1
_STOP
Res. Res. Res. Res. Res. Res. Res.
DBG_
I2C3
_STOP
DBG_
I2C2
_STOP
DBG_
I2C1
_STOP
Res. Res. Res. Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res.
DBG_
IWDG
_STOP
DBG_
WWDG
_STOP
DBG_
RTC
_STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
TIM2
_STOP
rw rw rw rw
Bit 31 DBG_LPTIM1_STOP: LPTIM1 stop in CPU1 debug
0: Normal operation. LPTIM1 continues to operate while CPU1 is in debug mode.
1: Stop in debug. LPTIM1 is frozen while CPU1 is in debug mode.
Bits 30:24 Reserved, must be kept at reset value.
Bit 23 DBG_I2C3_STOP: I2C3 SMBUS timeout stop in CPU1 debug
0: Normal operation. I2C3 SMBUS timeout continues to operate while CPU1 is in debug
mode.
1: Stop in debug. I2C3 SMBUS timeout is frozen while CPU1 is in debug mode.
Bit 22 DBG_I2C2_STOP: I2C2 SMBUS timeout stop in CPU1 debug
0: Normal operation. I2C2 SMBUS timeout continues to operate while CPU1 is in debug
mode.
1: Stop in debug. I2C2 SMBUS timeout is frozen while CPU1 is in debug mode.
Bit 21 DBG_I2C1_STOP: I2C1 SMBUS timeout stop in CPU1 debug
0: Normal operation. I2C1 SMBUS timeout continues to operate while CPU1 is in debug
mode.
1: Stop in debug. I2C1 SMBUS timeout is frozen while CPU1 is in debug mode.
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: IWDG stop in CPU1 debug
0: Normal operation. IWDG continues to operate while CPU1 is in debug mode.
1: Stop in debug. IWDG is frozen while CPU1 is in debug mode.
Bit 11 DBG_WWDG_STOP: WWDG stop in CPU1 debug
0: Normal operation. WWDG continues to operate while CPU1 is in debug mode.
1: Stop in debug. WWDG is frozen while CPU1 is in debug mode.
Bit 10 DBG_RTC_STOP: RTC stop in CPU1 debug
0: Normal operation. RTC continues to operate while CPU1 is in debug mode.
1: Stop in debug. RTC is frozen while CPU1 is in debug mode.
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 DBG_TIM2_STOP: TIM2 stop in CPU1 debug
0: Normal operation. TIM2 continues to operate while CPU1 is in debug mode.
1: Stop in debug. TIM2 is frozen while CPU1 is in debug mode.
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