RM0453 Rev 1 443/1461
RM0453 System configuration controller (SYSCFG)
445
11.2.15 SYSCFG radio debug control register (SYSCFG_RFDCR)
Address offset: 0x208
Reset value: 0x0000 0000
Bit 14 DMA2CH7IM: DMA2CH7 interrupt mask to CPU2
0: DMA2CH7 interrupt forwarded to CPU2
1. DMA2CH7 interrupt to CPU2 masked
Bit 13 DMA2CH6IM: DMA2CH6 interrupt mask to CPU2
Bit 12 DMA2CH5IM: DMA2CH5 interrupt mask to CPU2
Bit 11 DMA2CH4IM: DMA2CH4 interrupt mask to CPU2
Bit 10 DMA2CH3IM: DMA2CH3 interrupt mask to CPU2
Bit 9 DMA2CH2IM: DMA2CH2 interrupt mask to CPU2
Bit 8 DMA2CH1IM: DMA2CH1 interrupt mask to CPU2
Bit 7 Reserved, must be kept at reset value.
Bit 6 DMA1CH7IM: DMA1CH7 interrupt mask to CPU2
0: DMA1CH7 interrupt forwarded to CPU2
1. DMA1CH7 interrupt to CPU2 masked
Bit 5 DMA1CH6IM: DMA1CH6 interrupt mask to CPU2
Bit 4 DMA1CH5IM: DMA1CH5 interrupt mask to CPU2
Bit 3 DMA1CH4IM: DMA1CH4 interrupt mask to CPU2
Bit 2 DMA1CH3IM: DMA1CH3 interrupt mask to CPU2
Bit 1 DMA1CH2IM: DMA1CH2 interrupt mask to CPU2
Bit 0 DMA1CH1IM: DMA1CH1 interrupt mask to CPU2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RFTBSEL
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 RFTBSEL: radio debug test bus selection
0 Digital test bus selected on RF_ADTB[3:0]
1: Analog test bus selected on RF_ADTB[3:0]
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