Reset and clock control (RCC) RM0453
286/1461 RM0453 Rev 1
control/status register (RCC_CSR). The following frequency ranges are available: 1MHz,
2 MHz, 4 MHz (default value) and 8 MHz.
The MSI clock can be selected as system clock after a wakeup from Stop mode (Stop 0,
Stop 1 or Stop 2, see Section 7.3: Low-power modes). It can also be used as a backup clock
source (auxiliary clock for the CPUs) if the HSE32 crystal oscillator fails (see Section 7.2.10:
Clock security system on HSE32 (CSS)).
The MSI RC oscillator provides a low-power clock source. In addition, when used in PLL-
mode with the LSE, it also provides a very accurate clock source that can be used to feed
the PLL to run the system at the maximum speed 48 MHz.
The MSIRDY flag in the RCC clock control register (RCC_CR) indicates whether the MSI
RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by
hardware. The MSI RC can be switched on and off by using the MSION bit in the RCC clock
control register (RCC_CR).
Hardware auto calibration with LSE (PLL-mode)
When a 32.768 kHz external oscillator is present in the application, it is possible to configure
the MSI in a PLL-mode by setting the MSIPLLEN bit in the RCC clock control register
(RCC_CR). When configured in PLL-mode, MSI automatically calibrates itself thanks to the
LSE. This mode is available for all MSI frequency ranges.
Software calibration
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing
process variations. This is why each device is factory calibrated by ST for 1 % accuracy at
an ambient temperature T
A
= 25 °C. After reset, the factory calibration value is loaded in the
MSICAL[7:0] bits in the RCC internal clock sources calibration register (RCC_ICSCR). If the
application is subject to voltage or temperature variations, this may affect the RC oscillator
speed. The MSI frequency can be trimmed in the application using the MSITRIM[7:0] bits in
the RCC internal clock sources calibration register (RCC_ICSCR). For more details on how
to measure the MSI frequency variation, refer to Section 7.2.20: Internal/external clock
measurement with TIM16/TIM17.
7.2.4 PLL
The device embeds one PLL. The PLL provides up to three independent outputs. The
internal PLL can be used to multiply the HSI16, HSE32 or MSI output clock frequency. The
PLL input frequency must be between 2.66 and 16 MHz. The selected clock source is
divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the
requested input range. Refer to Figure 27: Clock tree and RCC PLL configuration register
(RCC_PLLCFGR).
The PLL configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0 in the RCC clock control register (RCC_CR).
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in the
RCC PLL configuration register (RCC_PLLCFGR).
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