RM0453 Rev 1 513/1461
RM0453 Extended interrupts and event controller (EXTI)
524
interrupt signal is activated. The EXTI_PR pending bit must be set to 1 by software. This
clears the it_exti_per(y) interrupt.
For direct event inputs, when enabled in the associated peripheral, an event request is
generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.
When the associated direct event is unmasked in EXTI_IM, the corresponding CPU sub-
system wakes up. The CPU is woken up (interrupted) by the peripheral synchronous
interrupt.
The CPU event must be unmasked in EXTI_EMR to generate an event. When the enabled
edges occur on the event input, a CPU event pulse is generated. There is no event pending
bit.
For the configurable event inputs, an event request can be generated by software, setting to
1 the corresponding bit in the interrupt/event register EXTI_SWIER. This allows the
generation of a rising edge on the event. The edge event pending bit must be set in
EXTI_PR, irrespective of the setting in EXTI_RTSR.
16.6 EXTI registers
The EXTI register map is divided in sections listed in the table below.
All these registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.
16.6.1 EXTI rising trigger selection register (EXTI_RTSR1)
Address offset: 0x000
Reset value: 0x0000 0000
Contains only register bits for configurable events.
Table 96. EXTI register map sections
Address Description
0x000 - 0x01C General configurable event [31:0] configuration
0x020 - 0x03C General configurable event [63:32] configuration
0x080 - 0x0BC CPU1 input event configuration
0x0C0 - 0x0FC CPU2 input event configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 Res. Res. Res. Res. RT16
rw rw rw
1514131211109876543210
RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
To Next Page
Loading...
Need help?
General
