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ST STM32WL5 Series User Manual

ST STM32WL5 Series
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General-purpose timer (TIM2) RM0453
842/1461 RM0453 Rev 1
Figure 203. Counter timing diagram, internal clock divided by 2
Figure 204. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
MS31190V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0003
0002
0001
0000
0001
0002
0003
0034 0035
MS31191V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CNT_EN
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow
0036 0035

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ST STM32WL5 Series Specifications

General IconGeneral
BrandST
ModelSTM32WL5 Series
CategoryMicrocontrollers
LanguageEnglish

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