RM0453 Rev 1 349/1461
RM0453 Reset and clock control (RCC)
364
7.4.40 RCC CPU2 AHB1 peripheral clock enable in Sleep mode register
(RCC_C2AHB1SMENR)
Address offset: 0x168
Reset value: 0x0000 1007
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res.
CRC
SMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DMA
MUX1
SMEN
DMA2
SMEN
DMA1
SMEN
rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: CRC clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: CRC clock enabled by the clock gating during CPU2 CSleep mode, disabled during CPU2
CStop mode
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: DMAMUX1 clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: DMAMUX1 clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode
Bit 1 DMA2SMEN: DMA2 clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: DMA2 clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: DMA2 clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode
Bit 0 DMA1SMEN: DMA1 clock enable during CPU2 CSleep and CStop modes
This bit is set and cleared by software.
0: DMA1 clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: DMA1 clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode
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