RM0453 Rev 1 977/1461
RM0453 Low-power timer (LPTIM)
981
28.7.8 LPTIM counter register (LPTIM_CNT)
Address offset: 0x01C
Reset value: 0x0000 0000
28.7.9 LPTIM1 option register (LPTIM1_OR)
Address offset: 0x020
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
CNT[15:0]
rrrrrrrrrrrrrrrr
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses
and verify that the two returned values are identical.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OR_1 OR_0
rw rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 OR_1: Option register bit 1
0: LPTIM1 input 2 is connected to I/O
1: LPTIM1 input 2 is connected to COMP2_OUT
Bit 0 OR_0: Option register bit 0
0: LPTIM1 input 1 is connected to I/O
1: LPTIM1 input 1 is connected to COMP1_OUT
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