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RM0453 Rev 1 1421/1461

RM0453 Debug support (DBG)

1448

38.12.2 DBGMCU configuration register (DBGMCU_CR)

Address offset: 0x004

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

DBG_

STANDBY

DBG_

STOP

DBG_

SLEEP

rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DBG_STANDBY: Allows debug in Standby mode

This bit does not influence CPU2 operation, CPU2 cannot be debugged in Standby mode

even when this bit is enabled.

0: Normal operation. All clocks are disabled and the domain powered down automatically in

Standby mode.

1: Automatic clock stop/power down disabled. All active clocks and oscillators continue to run

during Standby mode and the domain supply is maintained, allowing full debug capability. On

exit from Standby mode, a domain reset is performed.

Bit 1 DBG_STOP: Allows debug in Stop mode

This bit does not influence CPU2 operation, CPU2 cannot be debugged in Stop mode even

when this bit is enabled.

0: Normal operation. All clocks are disabled automatically in Stop mode.

1: Automatic clock stop disabled. All active clocks and oscillators continue to run during Stop

mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the

Stop mode exit state.

Bit 0 DBG_SLEEP: Allows CPU1 debug in Sleep mode

0: Normal operation. Processor clock is stopped automatically in Sleep mode.

1: Automatic clock stop disabled. Processor clock continue to run, allowing full debug

capability.

ST STM32WL5 Series User Manual

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