ST STM32WL5 Series User Manual

Inter-integrated circuit (I2C) interface RM0453
1094/1461 RM0453 Rev 1
Figure 298. Timeout intervals for t
LOW:SEXT
, t
LOW:MEXT
.
t
LOW:SEXT
(1)
Cumulative clock low extend time (slave device) - 25 ms
t
LOW:MEXT
(2)
Cumulative clock low extend time (master device) - 10 ms
1. t
LOW:SEXT
is the cumulative time a given slave device is allowed to extend the clock cycles in one message
from the initial START to the STOP. It is possible that, another slave device or the master also extends the
clock causing the combined clock low extend time to be greater than t
LOW:SEXT
. Therefore, this parameter is
measured with the slave device as the sole target of a full-speed master.
2. t
LOW:MEXT
is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device
or another master also extends the clock causing the combined clock low time to be greater than t
LOW:MEXT
on a given byte. Therefore, this parameter is measured with a full speed slave device as the sole target of
the master.
Table 231. SMBus timeout specifications (continued)
Symbol Parameter
Limits
Unit
Min Max
MS19866V1
Start Stop
t
LOW:SEXT
t
LOW:MEXT
t
LOW:MEXT
t
LOW:MEXT
Clk
Ack
Clk
Ack
SMBCLK
SMBDAT

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English