Low-power universal asynchronous receiver transmitter (LPUART) RM0453
1250/1461 RM0453 Rev 1
36.7.4 LPUART control register 3 (LPUART_CR3)
Address offset: 0x08
Reset value: 0x0000 0000
Bits 13:12 STOP[1:0]: STOP bits
These bits are used for programming the stop bits.
00: 1 stop bit
01: Reserved.
10: 2 stop bits
11: Reserved
This bitfield can only be written when the LPUART is disabled (UE = 0).
Bits 11:5 Reserved, must be kept at reset value.
Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the LPUART is disabled (UE = 0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bits 3:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG[2:0] RXFTIE RXFTCFG[2:0] Res. TXFTIE WUFIE WUS[1:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP DEM DDRE
OVRDI
S
Res. CTSIE CTSE RTSE DMAT DMAR Res. Res. HDSEL Res. Res. EIE
rw rw rw rw rw rw rw rw rw rw rw
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