ST STM32WL5 Series - Figure 197. Counter Timing Diagram, Internal Clock Divided by 1; Figure 198. Counter Timing Diagram, Internal Clock Divided by 2

General-purpose timer (TIM2) RM0453
838/1461 RM0453 Rev 1
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 197. Counter timing diagram, internal clock divided by 1
Figure 198. Counter timing diagram, internal clock divided by 2
36
34
33
32 31
30 2F
04
03
02 01 00
05
MS31184V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
(cnt_udf)
Update interrupt flag
(UIF)
35
MS31185V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0002
0001
0000
0036
0035
0034
0033