Reset and clock control (RCC) RM0453
330/1461 RM0453 Rev 1
7.4.26 RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2)
Address offset: 0x07C
Reset value: 0x0000 0061
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPTIM3SMEN
LPTIM2SMEN
Res. Res. Res. Res.
LPUART1SMEN
rw rw rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3SMEN: Low-power timer 3 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: LPTIM3 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: LPTIM3 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled
during CPU1 CStop mode
Bit 5 LPTIM2SMEN: Low power timer 2 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: LPTIM2 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: LPTIM2 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled
during CPU1 CStop mode
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1SMEN: Low-power UART 1 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: LPUART1 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: LPUART1 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled
during CPU1 CStop mode
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