ST STM32WL5 Series User Manual

RM0453 Rev 1 469/1461
RM0453 Direct memory access controller (DMA)
479
13.6.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
This register may mix secure and non secure information, depending on the secure mode of
each channel (SECM bit of the DMA_CCRx register).
A secure software is able to set any flag clear bit of the DMA_IFCR, and order DMA
hardware to clear any corresponding flag(s) in the DMA_ISR register.
A non-secure software is restricted to order DMA hardware to clear the non-secure flag(s) in
the DMA_ISR, by setting any non-secure corresponding flag clear bit(s) of the DMA_IFCR
register.
This register may mix privileged and unprivileged information, depending on the privileged
mode of each channel (PRIV bit of the DMA_CCRx register).
A privileged software is able to set any flag clear bit of the DMA_IFCR, and order DMA
hardware to clear any corresponding flag(s) in the DMA_ISR register.
An unprivileged software is restricted to order DMA hardware to clear the unprivileged
flag(s) in the DMA_ISR, by setting any unprivileged corresponding flag clear bit(s) of the
DMA_IFCR register.
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res.
CTEIF7
CHTIF7 CTCIF7
CGIF7
CTEIF6
CHTIF6 CTCIF6
CGIF6
CTEIF5
CHTIF5 CTCIF5
CGIF5
wwwwwwwwwwww
1514131211109876543210
CTEIF4
CHTIF4 CTCIF4
CGIF4
CTEIF3
CHTIF3 CTCIF3
CGIF3
CTEIF2
CHTIF2 CTCIF2
CGIF2
CTEIF1
CHTIF1 CTCIF1
CGIF1
wwwwww w w w w w w w w w w
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 CTEIF7: transfer error flag clear for channel 7
Bit 26 CHTIF7: half transfer flag clear for channel 7
Bit 25 CTCIF7: transfer complete flag clear for channel 7
Bit 24 CGIF7: global interrupt flag clear for channel 7
Bit 23 CTEIF6: transfer error flag clear for channel 6
Bit 22 CHTIF6: half transfer flag clear for channel 6
Bit 21 CTCIF6: transfer complete flag clear for channel 6

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English