Inter-integrated circuit (I2C) interface RM0453
1108/1461 RM0453 Rev 1
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter.
• In Slave mode with NOSTRETCH=0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
• If SMBus is supported (see Section 34.3: I2C implementation): the PEC transfer is
managed with the NBYTES counter. Refer to SMBus Slave receiver on page 1099 and
SMBus master receiver on page 1103.
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
34.4.18 Debug mode
When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_ configuration bits in the
DBG module.
34.5 I2C low-power modes
Table 236. Effect of low-power modes on the I2C
Mode Description
Sleep No effect. I2C interrupts cause the device to exit the Sleep mode.
Stop
(1)
1. Refer to Section 34.3: I2C implementation for information about the Stop modes supported by each
instance. If wakeup from a specific Stop mode is not supported, the instance must be disabled before
entering this Stop mode.
The I2C registers content is kept
(2)
. If WUPEN = 1 and I2C is clocked by an
internal oscillator (HSI16): the address recognition is functional. The I2C address
match condition causes the device to exit the Stop mode. If WUPEN=0: the I2C
must be disabled before entering Stop mode
2. In Stop 2 mode, only I2C3 register content is kept. The I2C1 and I2C2 instances are powered down and
must be reinitialized after exiting Stop 2 mode.
Standby
The I2C peripheral is powered down and must be reinitialized after exiting
Standby mode.
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