RM0453 Rev 1 129/1461
RM0453 Embedded Flash memory (FLASH)
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4.10.2 FLASH access control register 2 (FLASH_ACR2)
Address offset: 0x004
Reset value: 0x0000 0000 (Default)
Default reset when HDPAD = 0, 0x0000 0004 when HDPAD = 1
This register provides write access security and privilege. It can only be written by the
secure privileged CPU2. A write access from the unprivileged CPU2 or a CPU1 is ignored.
A non-secure or unprivileged write access generates an illegal access event. On any read
access, the register value is returned.
There are no read restrictions.
Note: When the system is non-secure (ESE = 0), this register cannot be written.
Bit 8 PRFTEN: CPU1 prefetch enable
0: CPU1 prefetch disabled
1: CPU1 prefetch enabled
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LATENCY[2:0]: Latency
These bits represent the ratio of the Flash HCLK clock period to the Flash memory access
time.
000: Zero wait state
001: One wait state
010: Two wait states
Others: reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C2SWDBGEN
HDPADIS
PRIVMODE
rw rw rw
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