Tamper and backup registers (TAMP) RM0453
1054/1461 RM0453 Rev 1
33.6.8 TAMP status clear register (TAMP_SCR)
Address offset: 0x3C
System reset value: 0x0000 0000
Bit 18 ITAMP3MF: Internal tamper 3 interrupt masked flag
This flag is set by hardware when the internal tamper 3 interrupt is raised.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3MF: TAMP3 interrupt masked flag
This flag is set by hardware when the tamper 3 interrupt is raised.
Bit 1 TAMP2MF: TAMP2 interrupt masked flag
This flag is set by hardware when the tamper 2 interrupt is raised.
Bit 0 TAMP1MF: TAMP1 interrupt masked flag
This flag is set by hardware when the tamper 1 interrupt is raised.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res.
C
ITAMP
8F
Res.
C
ITAMP
6F
C
ITAMP
5F
Res.
C
ITAMP
3F
Res. Res.
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Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CTAMP
3F
CTAMP
2F
CTAMP
1F
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Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CITAMP8F: Clear ITAMP8 detection flag
Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register.
Bit 22 Reserved, must be kept at reset value.
Bit 21 CITAMP6F: Clear ITAMP6 detection flag
Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.
Bit 20 CITAMP5F: Clear ITAMP5 detection flag
Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.
Bit 19 Reserved, must be kept at reset value.
Bit 18 CITAMP3F: Clear ITAMP3 detection flag
Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
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