Embedded Flash memory (FLASH) RM0453
128/1461 RM0453 Rev 1
4.10 FLASH registers
4.10.1 FLASH access control register (FLASH_ACR)
Address offset: 0x000
Reset value: 0x0000 0600
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EMPTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PES Res. Res. DCRST ICRST DCEN ICEN PRFTEN Res. Res. Res. Res. Res. LATENCY[2:0]
rw rw rw rw rw rw rw rw rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 EMPTY: Flash user area empty
When read, this bit indicates whether the first location of the user Flash is erased or has a
programmed value.
0: Read: user Flash programmed
1: Read: user Flash empty
Bit 15 PES: CPU1 program/erase suspend request
0: Flash program and erase operations granted
1: Any new Flash program and erase operation is suspended until this bit and the same bit in
FLASH_C2ACR are cleared. The PESD bit in FLASH_SR and FLASH_C2SR areset when
at least one PES bit in FLASH_ACR or FLASH_C2ACR is set.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 DCRST: CPU1 data cache reset
0: CPU1 data cache not reset
1: CPU1 data cache reset
This bit can be written only when the data cache is disabled.
Bit 11 ICRST: CPU1 instruction cache reset
0: CPU1 instruction cache not reset
1: CPU1 instruction cache reset
This bit can be written only when the instruction cache is disabled.
Bit 10 DCEN: CPU1 data cache enable
0: CPU1 data cache disabled
1: CPU1 data cache enabled
Bit 9 ICEN: CPU1 instruction cache enable
0: CPU1 instruction cache disabled
1: CPU1 instruction cache enabled
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