ST STM32WL5 Series User Manual

RM0453 Rev 1 81/1461
RM0453 Global security controller (GTZC)
96
Table 6. Memory access error generation
Memory
access
type
(1)
Hide protected
memory
(HDPADIS = 1)
Secure privileged
memory
Secure
unprivileged
memory
Non-secure
privileged
memory
Non-secure
unprivileged
memory
Access
Ila_event
Bus error
Access
Ila_event
Bus error
Access
Ila_event
Bus error
Access
Ila_event
Bus error
Access
Ila_event
Bus error
Secure
Privileged
Fetch
Illegal
No
Yes
Grant
No No
Grant
No No
Illegal
S
Yes
Illegal
S
Yes
Read
Yes
(2)
Grant
No No
Grant
No No
Write
Unprivileged
Fetch
P
(3)
Yes
Illegal
P
Yes
Illegal
S and P
Yes
Illegal
S
Yes
Read
No No
P
No
Grant
No No
Write
Non-secure
Privileged
Fetch
S
(4)
Yes
S
Yes
Illegal
S
Yes
Grant
No No
Grant
No No
Read
No No No
Write
Unprivileged
Fetch
S and P
(3)(4)
Yes
S and P
Yes Yes
Illegal
P
Yes
Read
No No No No
Write
Illegal and error event generated
Granted
1. Illegal: security infringement
S: ila_event due to illegal security infringement
P: ila_event due to illegal privileged infringement
S and P: ila_event due to secure and privileged infringement
2. Only for CPU accesses. A DMA access does not generate a bus error.
3. When hide protected area is privileged.
4. When hide protected area is secure.

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English