RM0453 Rev 1 337/1461
RM0453 Reset and clock control (RCC)
364
7.4.31 RCC control/status register (RCC_CSR)
Address offset: 0x094
Reset value: 0x0C01 C600
(Reset by NRST pad, except reset flags by POR only, not reset by wakeup from Standby)
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Bit 2 LSEBYP: LSE oscillator bypass
This bit is set and cleared by software to bypass the LSE oscillator. It can be written only
when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is
stable.
0: LSE oscillator not ready
1: LSE oscillator ready
Note: Once the LSEON bit is cleared, this bit goes low after six LSE clock cycles.
Bit 0 LSEON: LSE oscillator enable
This bit is set and cleared by software.
0: LSE oscillator off
1: LSE oscillator on
Note: The LSE clock is directly forwarded to the RTC. To enable the LSE clock to other
system peripherals (USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO,
MSI PLL mode), LSE must be enabled with the LSESYSEN bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR
RSTF
WWDG
RSTF
IWDG
RSTF
SFT
RSTF
BOR
RSTF
PIN
RSTF
OBLRS
TF
RFILA
RSTF
RMVF Res. Res. Res. Res. Res. Res. Res.
r r rrrr r rrw
1514131211109 8 765432 1 0
RFRST
RF
RSTF
Res. Res. MSISRANGE[3:0] Res. Res. Res.
LSI
PRE
Res. Res.
LSI
RDY
LSION
rw r rw rw rw rw rw r rw
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