ST STM32WL5 Series - Figure 133. Counter Timing Diagram, Internal Clock Divided by 4; Figure 134. Counter Timing Diagram, Internal Clock Divided by N

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Advanced-control timer (TIM1) RM0453

736/1461 RM0453 Rev 1

Figure 133. Counter timing diagram, internal clock divided by 4

Figure 134. Counter timing diagram, internal clock divided by N

0000

0001

0035

0036

MS31080V2

CK_PSC

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter overflow

Update interrupt flag

(UIF)

CNT_EN

MS31081V2